1. Field of the Invention
The present invention relates to a passive polyphase filter (complex filter) used for image rejection or the like in signal processing in electronic equipment, and particularly, the present invention relates to the improvement in a layout of components such as resistors, capacitors and input/output nodes.
2. Description of Related Art
A passive polyphase filter used for image rejection in signal processing in electronic equipment has a circuit structure as shown in FIG. 20 in the case of a 4-phase input, for example. The passive polyphase filter in FIG. 20 is configured by connecting resistors R1, R2, R3, R4 and capacitors Cl, C2, C3, C4 in a loop. I1, I2, I3 and I4 are input nodes through which signals are inputted, and O1, O2, O3 and O4 are output nodes through which signals are outputted. The resistors R1-R4 have the same resistance value, and the capacitors C1-C4 have the same capacitance value.
In the circuit in FIG. 20, as a signal processing from the input node I1 to the output node O1, a passive primary low-pass filter is configured by the resistor R1 and the capacitor C4, while as a signal processing from the output node O2 to the input node I1, a passive primary high-pass filter is configured by the capacitor C1 and the resistor R1. Namely, an inherent input signal and a signal from the output node O2 are synthesized at the input node I1 and the thus synthesized signal is outputted to the output node O1. The relationships of signals from the other signal input nodes to the output nodes are similar.
FIG. 21 is a plan view showing an example of a layout of the above-mentioned passive polyphase filter on an integrated circuit. The respective reference numerals are applied corresponding to the circuit diagram of FIG. 20. In this conventional layout of a passive polyphase filter, wirings 102-104 are made to meander in order to adjust the wiring resistance to be equal to that of the wiring 101 (see, for example, “IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL. 36, No. 6, JUNE 2001, CMOS Mixers and Polyphase Filters for Large Image Rejection, Farbod Behbahani et al.”).
FIG. 22 is a plan view showing a layout disclosed in JP 2003-234406 A (p. 7, FIG. 1) as another example of a conventional passive polyphase filter. In the layout of the conventional passive polyphase filter, the input node I1 and the input node I4 are shared, and also the input node I2 and the input node 13 are shared to provide a layout on an integrated circuit for a 2-phase input. The resistors R1-R4 and the capacitors C1-C4 have a 90-degree rotational symmetry, and the resistors and the capacitors are arranged alternately to reduce the occurrence of parasitic capacitors.
Conventionally in a layout of a passive polyphase filter used for image rejection in signal processing in electronic equipment, there have been some objects when providing the passive polyphase filter on an integrated circuit. Specifically, it is required to simplify the layout of plural stages, reduce influences on the characteristics by a parasitic element caused by the layout, and equalize the influences.
Therefore, for the case of a 4-phase input passive polyphase filter as shown in FIG. 21, wirings 102-104 are made to meander to match the values of the wiring resistance as a parasitic element caused by the wiring 101 connecting the resistor R1 and the capacitor C1, the wiring 102 connecting the resistor R2 and the capacitor C2, the wiring 103 connecting the resistor R3 and the capacitor C3, and the wiring 104 connecting the resistor R4 and the capacitor C4. As a result, the layout of the passive polyphase filter becomes complicated.
FIG. 23 is a circuit diagram showing a 2-stage 4-phase input passive polyphase filter. As an example of a layout of this passive polyphase filter on an integrated circuit, FIG. 24 shows a layout configured on the basis of the method as shown in FIG. 21. In this layout, for connecting the output nodes of the first stage and the input nodes of the second stage in the respective phases, a wiring 106 connecting the output O12 of the first stage and the input I22 of the second stage, a wiring 107 connecting the output O13 and the input I23, and a wiring 108 connecting the output O14 and the input I24 must be crossed with respect to a wiring 105 connecting the resistor R21 and the capacitor C21. This creates a wiring capacitor as a parasitic element whose value will change the filter characteristics.
In a layout of a 4-phase input passive polyphase filter as shown in FIG. 22, a relative variation is differentiated due to the difference in the directions between the resistors R1 and R3, and the resistors R4 and R2, and thus it is difficult to obtain the same resistance value. In addition to that, when the 2-stage 4-phase input passive polyphase filter as shown in FIG. 23 is configured on the basis of the layout manner in FIG. 22, the configuration will be complicated considerably as shown in FIG. 25.